As semiconductor manufacturing technology continues to evolve toward smaller design rules and higher integration densities (e.g., 14 nm technology node and beyond), integrated circuit devices and components become increasingly smaller, creating challenges in layout formation and device optimization. One type of integrated circuit device which provides effective CMOS scaling solutions for FET fabrication at, and below, the 14 nm technology node includes fin-shaped FET devices (referred to as FINFET). A FINFET is a three-dimensional transistor structure which comprises at least one vertical semiconductor fin structure formed on a substrate, a gate structure formed over a portion of the vertical semiconductor fin, and source/drain regions formed by portions of the vertical semiconductor fin extending from both sides of the gate structure. The portion of the vertical semiconductor fin that is covered by the gate structure between the source/drain regions comprises a device channel region of the FINFET device.
As with all FET technologies, different semiconductor FET devices within a given integrated circuit may be fabricated with different device characteristics, such as switching speed, leakage power consumption, etc., to optimize the operating characteristics the FET devices for target functions or applications. For instance, one design may increase switching speed for FET devices providing computational logic functions, and another design may decrease power consumption for FET devices providing memory storage functions. It is known in the art that modifying a threshold voltage (Vt) of an FET device can enhance performance characteristics of the FET devices for certain applications. Conventional approaches for modifying a threshold voltage of FET devices include doping portions of the device to enhance channel mobility, or other techniques that involve extra process steps such as masking, lithography and etching, which can complicate fabrication and consume time and resources.